Virtual memory may be used when the physical memory of a computer system is not large enough to hold all of the desired content. A virtual memory address is used to access the physical memory location where the content is stored. The physical memory location may be identified by a physical memory page (by specifying a base address of the physical memory page) and an offset within the physical memory page. The relationship between the virtual memory address and the corresponding physical memory address is stored in a page table.
The virtual memory page-translation mechanism enables system software to create separate address spaces for each process or application. These address spaces are known as virtual address spaces. The system software uses the paging mechanism to selectively map individual pages of physical memory into the virtual address space using a set of hierarchical address-translation tables known collectively as page tables. Virtual memory may be implemented with any processor, including, but not limited to, a central processing unit (CPU), a graphics processing unit (GPU), and an accelerated processing unit (APU).
The page table footprint (size of the page table) to map a large memory space can become significant in size. One exemplary system contains 4 KB, 64 KB, and potentially larger page sizes. With the current page table format, a page table footprint is created that assumes that all page sizes are 4 KB. For example, a non-sparse 16 GB memory mapped using 4 KB pages requires 32 MB of space to store the page table. But if all the pages were 64 KB pages and if 64 KB page table entries (PTEs) could be stored natively in the page table, the page table size could be reduced to 8 MB.
Because the virtual memory space is larger than the physical memory of a system, some of the virtual memory might not be mapped (referred to discontiguous regions of mapped memory). Using a multiple-layer page table allows a smaller page table footprint by not mapping some areas of the virtual memory. In one example implementation, the x86 (CPU) processor page table format allows only three sizes of page tables: 4 KB, 2 MB, and 1 GB. To support the 2 MB and 1 GB formats, there is a bit indicating that the next level is not a page table block, but rather another PTE. In contrast, a flat page table means that the entire virtual memory address range would need to be mapped.
The table may be cached, for example, in a translation look-aside buffer (TLB). For caching, it is better to use larger pages. One example GPU virtual memory scheme uses fragments (which may be larger or smaller than a full page in size), which addresses the caching problem (by using larger page sizes), but not the page table footprint problem.